INQUIRYHow to reduce the parasitic conduction effect caused by Miller capacitance
Release time:2024-08-30
One problem commonly encountered when IGBTs are switched is the Miller plateau during turn-on of the parasitic Miller capacitance. The Miller effect is very obvious in the application of single supply gate drive. Due to the coupling between the gate G and the collector C, a very high transient dv/dt will be generated during the turn-off period of the IGBT, which will cause the voltage between the gate VGE to rise and turn on, which is a potential risk.
In the half-bridge topology, when the upper IGBT(S1) is conducting, a varying voltage dV/dt is applied across the lower IGBT(S1)C-E. Current flows through the parasitic Miller capacitor CCG of S2, the gate drive resistor RG, and the internal integrated gate drive resistor RDRIVER. The magnitude of the current can be roughly estimated by the following formula:
This current produces a voltage difference across the gate resistance, which, if it exceeds the gate drive threshold of the IGBT, will result in parasitic conduction. Design engineers should be aware that an increase in IGBT temperature will cause the IGBT gate drive threshold to decrease, usually in the order of mv/℃.
When the lower IGBT(S2) is turned on, the turn-on caused by the parasitic Miller capacitance will also occur at S1.
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